The below figure is waveform from GTKWAVE generated by iverilog. Here, clk period = 2ns, LeftIn = 1, RightIn = 1 Time (ns) Usr_nbit_tb.v is test bench for usr_nbit.v with following values for corresponding time. In this example I used size=4 which means 4 bit universal shift register.
The parameter size can be changed as per requirements. usr_nbit is the instantiated module of universal_shift_register_1bit, with variable size.
The usr_nbit.v contain 2 module universal_shift_register_1bit and usr_nbit. This is 1-bit Universal Shift Register, written using Flip-Flop with case statement (universal_shift_register_1bit). OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow. This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK.
